数字锁相环的参数设计及其应用

The Parameter Design of the Digital Phase Lock Loop and Its Application

数字锁相环路(DPLL)是数字相干解调技术的核心。根据锁相环理论,分析了在最小等效噪声带宽、最小相位均方误差以及最短锁定时间三种意义上的参数优化设计方案,并给出了简明的、具有一定工程指导意义的结果。该结果在应用了Intel公司解调芯片STEL-2105的系统中获得了具体应用。

The Digital Phase Lock Loop(DPLL)is the core of the coherent demodulation.Based on the theory of PLL,this paper present s a brief analysis on three optimized plans including the minimum equi-valent noise bandwidth,the minimum phase mean -square error and the mini mum lock time.Several con-cise results are given,which can gui de engineering design in this area.I ntel Corporation finds application s in our system using STEL -2105,which is a demodulation chip made.