20万门CMOS门阵列设计技术

Design Technologies of 200K CMOS Gate Array

本文主要介绍 0 8μmCMOS门阵列的设计技术 ,包括建库技术 ,可测性设计技术、时钟设计技术、电源、地设计技术、电路结构优化、余量设计技术等 ,最后介绍了 2 0万门母片及电路的主要参数。

In this paper,design technologies of 0 8 micron CMOS gate array,such as building library,testability,clock design,power ground design,architecture optimizing and margin design,are presented.The key parameters of the base and circuit of 200K gate array are also given.