高速路由器缓冲区流水工作算法设计与实现

Design and Implementation of a Pipelining Buffer Algorithm for High-Speed Routers

本文根据IPOA的思想 ,提出流水工作算法在缓冲中将信元重组成IP报文 ,从而有效地解决了信元写入时产生拥塞的问题 ,同时还介绍了读出报文时可以采用的两种调度算法 :均衡调度算法和非均衡调度算法。本文最后以具体的路由器为背景 。

According to the idea of IPOA,this paper presents a pipelining algorithm in buffer management which is used to reassemble ATM cells into IP packets In this way,the problem of congestion when cells are written is avoided Besides,this paper introduces two scheduling algorithms used in packet reading:fair and unfair Finally the paper takes the router in use as the background,and implements the design with FPGA