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混合电压I/O电路的ESD保护结构研究

The investigation of ESD protection for mixed-voltage I/O
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摘要 给出了混合电压 I/O电路坚固的 ESD保护结构,它是由放大器结构的 NMOS晶体管组合而成。这个保护电路由硅化物和硅化物隔离两种工艺研制而成。为了确保硅化物器件指状触发的一致性,增加了栅电压调节电路,研究电路的设计规则以避免产生寄生的击穿路径。 We demonstrate that NMOS transistors stacked in a cascode configuration provide robust ESD protection for mixed voltage I/O in both silicided and silicide-blocked technologies. Circuits for gate voltage modulation were added to ensure uniform finger triggering of the fully silicided device. Layout and circuit rules were developed to avoid parasitic breakdown paths.
出处 《微处理机》 2002年第1期19-22,共4页 Microprocessors
关键词 静电放电 混合电压I/O电路 硅化物工艺 ESD保护结构 集成电路 ESD, mixed - voltage circuit,stacked NMOS,silicided technology, HBM
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参考文献4

  • 1[1]Voldman SH.ESD protection in a mixed voltage interface and multi-rail disconnected power grid environment in 0.50 and 0.25um channel length CMOS technologies.in:EOS/ESD symposium proceedings.1994:125-34
  • 2[2]Krakauer D,Mistry K.ESD protection in a 3.3Vsubmicron silicided CMOS technology.In:EOS/ESD symposium proceedings.1992:250-7
  • 3[3]Anderson WR.Circuit and process design considerations for ESD protection in advanced CMOS processes.Microelectron Reliab 1997;37:1083-103
  • 4[4]Timothy J,Maloney.Designing MOS inputs and outputs to avoid oxide failure in the charged device model.In:EOS/ESD Symposium proceedings,1998:220-7

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