VHDL及其在数显频率计中的应用

VHDL and its application in frequency meter with digital display

介绍了标准化硬件描述语言VHDL的结构模型及其自顶向下的设计方法,并将此方法应用于数显频率计的设计中,最后将结果与传统的设计进行了对比,总结出用VHDL设计的优点并对其应用前景做了展望.

Presents the structure models and design methods from top to bottom of Very High Speed Integrated Circuit Hardware Description Language (VHDL). VHDL is used in the design of frequency meter with digital display. In the end, the results are compared with the traditional design, and the advantages of using VHDL design are summarized, and its application prospects are sketched out.