用于加法器的功耗延迟积优化混合进位算法

A Hybrid Carry Algorithm for Power Delay Product Optimization Applied in Adders

为了实现高性能的加法器,提出了面向功耗延迟积(PDP)优化的混合进位算法。该算法能快速搜索加法器的混合进位,以优化PDP。采用超前进位算法和行波进位算法交替混合,兼具超前进位算法速度快和行波进位算法功耗低的特点。该算法采用C语言实现并编译,结果应用于MCNC Benchmark电路,进行判定测试。与应用三种传统算法的加法器相比,应用该算法的加法器在位数为8位、16位、32位和64位时,PDP改进量分别为40.0%、70.6%、85.6%和92.9%。

In order to design a high performance adder,a hybrid algorithm based on mixed-carry adder for power delay product optimization was proposed.The algorithm could search rapidly the mixed-carry of adders to optimize the power delay product.The advantages of carry look ahead adder algorithm and ripple carry adder algorithm were applied alternately to the new adder by combining CLA algorithm with RCA algorithm.The proposed algorithm was implemented and compiled in C language,and the results were applied to MCNC Benchmark circuit for decision testing.Compared with three traditional adder algorithms,the proposed algorithm had an increment of power delay product (PDP)of 40.0%,70.6%,85.6%and 92.9%respectively when the adder was 8bit,16bit,32bit and 64 bit.