期刊文献+

基于猴群算法的3D NoC IP核测试优化方法 被引量:1

IP Cores Test Optimization Method of 3D NoC Based on Monkey Algorithm
下载PDF
导出
摘要 如何对三维片上网络(three Dimensional Network-on-Chip,3DNoC)资源内核的测试进行优化以缩短测试时间,提高资源利用率是当前3DNoC测试面临的主要问题之一.本文针对3DNoC IP核测试优化问题,开展TSV位置与IP核测试数据分配方案协同优化研究.在带宽、功耗和TSV数量约束下,将TSV位置方案和IP核测试数据分配方案作为寻优变量,采用猴群算法进行寻优.算法通过爬和望跳过程进行局部搜索并结合翻过程在不同领域进行搜索从而找到最优解,加入精英保留策略以确保算法收敛性,使算法搜索结果更为准确.以ITC’02电路为实验对象,实验结果表明,该算法能够有效地优化3DNoC资源分配,缩短测试时间,提高资源利用率. How to optimize the test of the three-dimensional network-on-chip (3D NoC)resource core to shorten test time and increase resource utilization is one of the major problems that the 3D NoC testing faced.This work focuses on 3D NoC IP core test optimization issues,and conducts collaborative optimization research on TSV location and IP core test data distribution schemes.Under the constraints of bandwidth,power consumption and TSV quantity,the TSV location scheme and IP core test data distribution scheme are used as optimization variables and Monkey Algorithm(MA)is used to optimize.The algorithm performs local search through the climb and watch-jump process and searches in different fields with the somersault process to find the optimal solution-The elite retention strategy is added to ensure the convergence of the algorithm and the algorithm search result is more accurate.Taking the ITC'02circuit as the experimental object,the experimental results show that the algorithm can effectively optimize the 3D NoC resource allocation,shorten the test time,and improve resource utilization.
作者 许川佩 陈玄 XU Chuan-pei;CHEN Xuan(School of Electronic Engineering and Automation,Guilin University of Electronic Technology,Guilin 541004,China;Guangxi Key Laboratory of Automatic Detection Technology and Instrument,Guilin 541004,China)
出处 《微电子学与计算机》 北大核心 2019年第1期22-26,31,共6页 Microelectronics & Computer
基金 国家自然科学基金(61561012)
关键词 三维片上网络 IP核测试优化 猴群算法 three-dimensional network-on-chip(3D NoC) IP core test optimization monkey algorithm
  • 相关文献

参考文献5

二级参考文献57

  • 1欧阳一鸣,刘蓓,齐芸.三维片上网络测试的时间优化方法[J].计算机研究与发展,2010,47(S1):332-336. 被引量:4
  • 2许川佩,王征,李智.基于量子进化算法的SoC测试结构优化[J].仪器仪表学报,2007,28(10):1792-1799. 被引量:4
  • 3DeBenedictis E P. Will moore′s law be sufficient[A].Pittsburgh:ACM,2005.45-56.
  • 4C Anshuman,C Krishnendu. Test data compression and decom-pression based on internal scan chains and Golomb coding[J].{H}IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2002,(06):715-722.
  • 5P T Gonciari,B Al-Hashimi. Improving compression ra-tio,area overhead,and test application time for system-on-a-chip test data compression/decompression[A].Paris:ACM,2002.604-611.
  • 6Erik Larsson,Klas Arvidsson. Efficient test solutions for core-based designs[J].{H}IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2004,(05):758-775.
  • 7Krishnendu Chakrabarty. Test scheduling for core-based systems using mixed-integer linear programming[J].{H}IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2000,(10):1163-1174.
  • 8Sandeep Korann. On test scheduling for core-based SoCs[A].Baugalore:ACM,2002.505-510.
  • 9Gang Zeng,Hideo Ito. Concurrent core test for test cost reduc-tion using merged test set and scan tree[A].San Jose:IEEE,2005.143-146.
  • 10M Alexandre,Amory Frederico Ferlini. DfT for the reuse of networks-on-chip as test access mechanism[A].Berkeley:IEEE,2007.435-440.

共引文献32

同被引文献15

引证文献1

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部