基于FPGA的百兆以太网RGMII接口设计

Design of fast Ethernet RGMII interface based on FPGA

随着互联网技术的日益发展,越来越多的数据通过以太网进行传输。以太网传输速率也从10 Mb/s提高到100 Mb/s,再到1 000 Mb/s和10 Gb/s。而百兆以太网以其独特的高速实用特性走进千家万户和诸多应用场景。基于此,本文致力于设计一种百兆以太网的RGMII通用接口。以Altera的Cyclone IV FPGA为核心,采用Marvell 88E1111作为PHY芯片,并配置为RGMII工作模式,通过对以太网帧前同步码进行完善和定位,并对数据格式和参考时钟进行转化,实现了从PHY对百兆以太网数据进行接收和处理,最后从PHY通过RGMII模式进行网络数据输出。测试中发送端采用了分辨率1 280 p×720 p,帧率25 fps,码率上限2 048 Kbps的高清网络视频流,经过本设计接口转发,在接收端接收的高清视频清晰无卡顿,wireshark抓包和ping包丢包率均为0。

With the increasing development of Internet technology, more and more data is transmitted via Ethernet. The Ethernet transmission rate has also been increased from 10 Mb/s to 100 Mb/s to 1 000 Mb/s and 10 Gb/s. And fast Ethernet has entered into millions of homes and many application with its unique high-speed and practical features. For that, this design is devoted to designing a 100 M Ethernet RGMII universal interface. This design takes Altera Cyclone IV FPGA as the core, uses Marvell 88 E1111 as the PHY chip, and configures it in the mode of RGMII. By completing and positioning the Ethernet frame preamble and converting the data format and reference clock, it realizes the reception of Fast Ethernet data from the PHY and the data processing, and finally outputs the network data to the PHY in RGMII mode. In the test, the send-end adopts a high-definition network video stream with a resolution of 1 280 p×720 p, a frame rate of 25 fps, and a code rate of 2 048 Kbps. After this design interface forwarding, the high-definition video received at the receive-end is clear and uncluttered, and the packet loss ratios of capture in wireshark software and ping packet are all zero.