嵌入式GPU中U型存储布局tile缓存的设计与实现

Design and implementation of embedded GPU tile buffer with U-Order layout

针对嵌入式GPU tile缓存在线性布局和Z型布局写回时由于地址跨度大而导致cache频繁冲突缺失的问题,设计了一种支持多级U型存储布局的tile缓存,使像素数据写回的地址连续,减少cache的冲突缺失,提高cache命中率.实验结果表明,当配置不同尺寸的tile缓存时,U型布局相对于线性布局cache命中率提高4%～13%,相对于Z型布局cache命中率提高1%～9%.

Aiming at solving the problem that cache frequent conflict misses in linear layout and Z-layout write back of embedded GPU tile buffer caused by the large address spans, a tile buffer supporting multi-level U-layout is designd,which makes the address continuous when the pixel data is written back, reduces the cache conflict misses and improves the cache hit rate. The experimental results show that when configuring tile buffers of different sizes, the U-layout improves the hit rate by 4%~13% compared to the linear layout cache, and increases the hit rate by 1%~9% compared to the Z-layout.