摘要
CPLD/FPGA面向速度或面向面积进行优化设计,在大多数情况下这两种选择是矛盾的。对速度进行优化设计,需要较多资源;对面积进行优化往往会导致系统速度降低。本文提出采用流水线设计、资源共享和预进位处理的方法解决了这个问题。
In the most cases,optimization design in CPLD/FPGA in speed and area are incompatible.More resource is needed in optimization design in speed;system speed usu-ally is reduced in optimization design in area.The problem can be solved by the offered method in this paper,which pipelining design,resource sharing and carry beforehand process are used.It is served as the technicians.
出处
《电测与仪表》
北大核心
2002年第2期42-44,共3页
Electrical Measurement & Instrumentation
