千兆以太网同步检测集成电路设计

Gigabit-Ethernet synchronization detector integrated circuit

采用两级分接电路结构 ,并将同步码字检测电路置于其间 ,设计了千兆以太网同步检测集成电路 .实现 1 .2 5Gb s速率的千兆以太网数据由 1路到 1 0路的串并转换以及同步码字的检测 .分析了RC网络效应对超高速集成电路中互连线的影响 ,基于TSMC 0 .35 μmCMOS工艺建立电路模型 .使用Smartspice工具在不同温度 ( 0～ 70℃ )、电源电压 ( 3.1 5～ 3.45V)及输入信号等条件下进行仿真 .结合版图参数提取后仿真的比较 ,证明了该设计在减小规模 ,简化结构和加快仿真流程方面的有效性 .

This paper presents a structure of comma-detector in cascade DEMUX to the achievement of 1.25 Gb/s operations including 1:10 demultiplexer, comma detection and word alignment logic. Considering the serious RC network effects of interconnections in very high speed digital ICs, the parasitic parameters of the interconnections with TSMC 0.35 μm CMOS process were extracted and added into the netlist. The re-simulations were compared at different temperature (0-70°C), various power supply voltages (3.15-3.45 V) and various input signal with Smartspice. The layout was finished in full custom. This structure can improve the design efficiency and reduce the circuit scale.