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模拟退火算法在低功耗BIST中的应用 被引量:6

Simulated annealing algorithm applied in low power BIST scheme
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摘要 提出了应用模拟退火算法在一定长度的测试矢量集中寻找有效测试矢量的近似最优分组 ,在尽量减少面积开销的同时减少有效测试矢量的个数 ,并且通过置入种子的方法使LFSR产生近似最优分组的矢量 ,因此在保障故障覆盖率的前提下达到了降低测试功耗的目的 .实验表明 ,采用此方法可降低测试功耗 70 %以上 ,而故障覆盖率维持不变 .此外 ,由于减少了测试矢量 ,测试时间也大为缩短 ,在实时系统中 。 An approach to approximately optimal group test vectors in a certain length of test patterns is proposed to decrease the number of test vectors based on simulated annealing algorithm. By the scheme of reseeding, this approach makes linear feedback shift register (LFSR) generate optimized groups of vectors, so as to reduce the power consumption without any loss of fault coverage. The experiment result shows that more than 70% power consumption can be reduced while keeping the fault coverage invariable. In addition, the test time is greatly shortened with decreased number of test vectors, which is important in real time device.
出处 《东南大学学报(自然科学版)》 EI CAS CSCD 北大核心 2002年第2期177-180,共4页 Journal of Southeast University:Natural Science Edition
基金 国家自然科学基金资助项目 (60 1760 18)
关键词 模拟退火算法 内建自测试 低功耗BIST 可测性设计 集成电路 故障覆盖率 low power consumption stimulated annealing BIST
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参考文献7

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同被引文献13

  • 1陈卫兵.一种新的低功耗BIST测试生成器设计[J].电子质量,2004(11):62-63. 被引量:4
  • 2陈卫兵,刘文艳.折叠控制器的低功耗改进设计[J].电子质量,2005(2):7-9. 被引量:1
  • 3李杰,李锐,杨军,凌明.基于部分扫描的低功耗内建自测试[J].固体电子学研究与进展,2005,25(1):72-76. 被引量:2
  • 4Zorian Y.A distributed BIST control scheme for complex VLSI devices[A].In:1993 VLSI Test Symposium,Digest ofPapers,Eleventh Annual 1993 IEEE[C].Atlantic City,NJ,1993,4-9.
  • 5Manich s,Gabarro A,Lopze M,Figueras J,Girard P,Guiller L,Landrault C,Pravossoudovitch S,Teixeira P,Santos M.Low Power BIST by Filtering Non-Detecting Vectors[C].Test Workshop 1999.Proceeding.European.1999,165-177.
  • 6Girard P,Guiller L,Landrault C,Pravossoudovitch S.A Test Vector Ordering Technigue for Switching Activity Reduction during Test Operation[C].In:IEEE Great Lakes Sympon VLSI,March 1999,24-27.
  • 7Girard P,Guiller L,Landrault C,Pravossoudovitch S.An Adjacency-Based Test Pattern Generator for Low Power BIST Design[C],IEEE 2000,459-464.
  • 8R.A.Rutenbar.Simulated annealing algorithms:an overview.IEEE Circuits and Devices Magazine,1989(5):19-26.
  • 9P.Girard,L.Guiller,C.Landrault,et al.A test vector inhibiting technique for low power BIST design.IEEE VLSI Test Symposium,1999,pp.407-412
  • 10梁华国,聚贝勒.海伦布昂特,汉斯-耶西姆.冯特利希.一种基于折叠计数器重新播种的确定自测试方案[J].计算机研究与发展,2001,38(8):931-938. 被引量:44

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