面向低功耗BIST的VLSI可测性设计技术

Testing Techniques of Low Power BIST for VLSI

随着手持设备的兴起和芯片对晶片测试越来越高的要求 ,内建自测试的功耗问题引起了越来越多人的关注。本文对目前内建自测试的可测性设计技术进行了分析并对低功耗的 VL SI可测性设计技术的可行性和不足分别进行了探讨。在文章的最后简单介绍了笔者最近提出的一种低功耗

With the fast growing portable electronics market and higher need of wafer test, power consumption problem of built in self test (BIST) has attracted more and more considerations. In this paper, we present a survey of the lower power testing techniques of build in self test (BIST) for VLSI systems and explored the present techniques along with their advantages and disadvantages.