快速乘法器中高速4-2压缩器的设计(英文)

A Design of High-Speed 4-2 Compressor for Fast Multiplier

文章给出了两种优化的4-2压缩器电路结构,一种是选用不同结构的异或门电路对传统的异或门4-2压缩器结构进行优化,另一种是通过单值到双值逻辑的转换用传输门搭建的4-2压缩器电路。基于0.35μm和0.25μmCMOS模型参数的SPICE模拟,对两种4-2压缩器电路的最大延迟、功耗和面积进行了比较。结果表明,和库综合的4-2压缩器相比,文章的设计对提高乘法器速度减小面积是有效的。

This paper describes two optimized 4 2 compressor circuit structures. One is the conventional XOR structure but is optimized and constructed by different XOR circuits,the other is composed of transmission gates(TG) and used single to dual rail circuit design methods. According to a circuit simulation with 0.35um and 0.25um CMOS process parameters,the maximum propagation delay,the power consumption and the layout area of the designed 4 2 compressors are obtained and compared. It shows that the designed 4 2 compressors can be optimized for high speed and small size applications when compared with the synthesized results.