30兆赫采样频率的采样-保持电路和减法-增益电路的误差分析及设计

Error Analyzing and Design of A 30 M Sample/s Sampling-holding Circuit and Subtract-gain Circuit

介绍一种 1 0位分辨率、3 0 MHz采样频率流水线操作 A/D变换器中的 CMOS全差分采样 -保持(S/H)电路和级间减法 -增益 (SUB/GAIN)电路的设计。首先概述这种电路在流水线 ADC中的作用和工作原理 ,然后逐一讨论它的各种误差源对整体精度的影响。在此基础上通过理论分析和计算机辅助分析 ,完成电路的优化设计。最后用 HSPICE软件对优化后的电路仿真 。

The design of a fully differential CMOS sampling holding circuit and inter stage subtract gain circuit used in 10 bit 30 M sample/s pipelined ADC is presented in this paper. Firstly the paper summarizes the principles of S/H and SUB/GAIN circuits; secondly it discusses the error sources in the circuit and its effect on total ADC one by one. Then the design and optimization are described. Finally the simulation results prove its performance meeting design specification.