一种低功率分层运动估值器的VLSI结构设计

A VLSI architecture for low power hierarchical motion estimator

本文提出一种新的低功率分层运动估值器的VLSI结构,它支持低比特视频编码器的高级预测模式,如H.263和MPEG-4。为减少芯片尺寸及功率消耗,在所有搜索层中使用同一个基本的搜索单元 (BSU)。另外,通过对数据流的有效控制,使其在高级预测模式下,在获得宏块运动矢量的同时,也获得每个宏块中的4个88子块的运动矢量。实验结果表明,这种结构采用较少的门电路,有效降低了功率消耗,并且实现了与全搜索块匹配算法(FSBMA)相似的编码效果,可广泛应用于无线视频通信所需的低功率视频编码器中。

In this paper we propose a new low power hierarchical motion estimator VLSI architecture that supports the advanced prediction mode of recent low bit-rate video coders such as H.263 and MPEG-4. In the proposed VLSI architecture, a basic searching unit (BSU) is commonly utilized for all hierarchical levels to make a low power and small sized motion estimator. Also, since the proposed architecture provides a scheduled data flow, both a macroblock-based motion vector (MV) and four block-based MVs per macroblock can be simultaneously obtained for the advanced prediction mode. The result shown, the proposed motion estimator provides similar coding performance as that of the full search block matching algorithm (FSBMA), and can be widely used in low power video encoder forapplication of wireless communicate.