一种高速实时定点FFT处理器的设计

The Design of a High Speed Real-time and Fixed-point FFT Processor

本文讨论了采用FPGA和ASIC硬件实现高速实时FFT处理器的设计方案,作者在这种高速FFT设计时选择的特点基于Radix 4 DIT算法、采用乒乓RAM的设计思路以及级与级间采用流水结构。另外由于FFT基4运算的复杂性,所以在设计基4运算单元、数据通道中串并转换、运算数据的拉齐、颠倒位序、双地址发生等方面也有一些特点。整体上考虑是:尽可能地能够进行高速的FFT运算,本文针对1024点、16 bits位长、定点数、复数点进行运算;考虑到芯片外围接口的问题,希望外围能够尽量方便用户使用,所以在外围数据、状态和控制线上比较精简,从而把复杂的控制部分转移到芯片内部实现。

The design method of a high speed real-time FFT processor using FPGA and ASIC technology is presented. It is based on the R4 DIT algorithm, Ping-pong RAM design and pipeline structure between stages. Several techniques, such as serial to parallel transform in the data-path, Synchronization of operating data, reverse address sequence, dual address generating etc, are employed to reduce the computing complexity of FFT Radix 4 algorithm. The main purpose of using these techniques is to accelerate the high speed FFT calculation as fast as possible. As an example, the high speed FFT calculation for 1024 points, 16 bits width, fixed-point, complex data is considered. To make peripheral interfaces to be handled easily by the user, peripheral data, status and control lines have been simplified and those complex control circuits are re-located to the interior of the chip.