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MPEG2专用视频解码VLSI中的控制策略 被引量:1

A Decentralized Control Scheme of Dedicated MPEG2 Video VLSI Decoder
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摘要 本文提出了一种新的适用于MPEG2专用视频解码芯片的控制策略:分散控制。该方案完全由各功能模块相互协调控制整个视频解码过程,而不需要总体控制,它满足对MPEG2视频规定的所有级别尤其是MP@HL进行实时解码的要求。与总体控制方式比较,分散控制机制对视频解码各功能模块没有严格的时间限制,可根据具体解码任务特性设计模块从而达到局部性能最优;同时分散控制过程简单,解码效率高,而且连接各功能模块间的缓存相当小,可大幅度的减小芯片的硬件开销,使得系统整体性能最优。 A novel decentralized control scheme of dedicated MPEG2 video decoder is presented. The processes of decoding video signals are distributively controlled by functional units in stead of the central controlling unit. All levels, especially MP@HL, of MPEG2 video signals are decoded on real time. Compared with the central control scheme, our strategy of controlling relaxes the time restrict for functional units as to optimize their design to respective specific decoding tasks. On the other hand, the simple process of decentralized control leads to higher efficiency, less hardware and, in the end, the best overall performance.
出处 《电路与系统学报》 CSCD 2002年第1期78-82,共5页 Journal of Circuits and Systems
基金 浙江省综合信息网技术重点实验室资助项目
关键词 MPEG2 视频解码 VLSI 控制策略 专用集成电路 MPEG2 video Control MP@HL decoding
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参考文献4

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同被引文献13

  • 1刘鹏 杨伟建 姚庆栋.基于RISC核的系统集成芯片协同仿真[A]..中国电子学会电路与系统学会第16届年会(ICCAS2001)[C].宁波,2001.5.
  • 2Lin Chia-Hsing, et al. On the Bus Arbitration for MPEG 2 Video Decoder. Proceedings of Technical Papers[A]. International Symposium on VLSI Technology, Systems, and Applications[C]. 1995, 201-205.
  • 3Ling Nam, et al. A Bus-Monitoring Model for MPEG Video Decoder Design[J]. IEEE Transactions on Consumer Electronics, 1997, 43(3):526-530.
  • 4Li Jui-Hua, et al. Architecture and Bus-Arbitration Schemes for MPEG-2 Video Decoder[J]. IEEE Transactions on Circuits and Systems for Video Technology, 1999, 9: 727-736.
  • 5Khayat S H, et al. A Proposed Bus Arbitration Scheme for Multimedia Workstations[A]. Proceedings of the International Conference on Multimedia Computing and Systems[C]. 1994: 415-423.
  • 6Yu Zhenghua, et al. Design and Implementation of HDTV Source Decoder[J]. IEEE Transactions on Consumer Electronics, 1998, 44: 384-387.
  • 7Kim Hansoo, et al. Multi-thread VLIW processor architecture for HDTV decoding [A]. Custom Integrated Circuits Conference[C]. 2000, 559-562.
  • 8Yarnauchi, et al. Single chip video processor for digital HDTV[J]. IEEE Transactions on Consumer Electronics, 2001, 47(3): 394-404.
  • 9Mao Xun, et al. A High Efficient Simulation Environment for HDTV Video Decoder in VLSI Design[A]. Proceedings of SPIE[C]. 2002, 4671.
  • 10Liu Peng, et al. Hardware/Software Codesign for HDTV Source Decoder on System Level[A]. Proceedings of SPIE[C]. 2002, 4671 : 679-686.

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