一种高速低功耗ECL多模分频器的设计

Design of a High-Speed Low-Power ECL Multimode Frequency Divider

本文介络一种高速低功耗ECL多模分频器的电路原理、电路和版图设计特点、工艺技术及研制结果。该分频器设计了0.5mA的内部开关电流和350mV的内部逻辑摆幅,输入输出均采用互补驱动。电路分频模数多,频率高,功耗低,典型功耗75mW,为相同集成度的普通ECL电路功耗的1/30～1/40。该电路广泛用于通讯、仪器仪表和频率合成器等领域。

A description of the principle, characteristics of circuit and layout design for a high-speed low-power ECL multimode frequency divider is presented, and process and experimental results for the device are also given in the paper. An internal switching current of 0.5mA and an internal logic swing of 350mV are designed for the divider, and complementary drive is adopted for both input and output.With multi frequency division mode and high frequency, this circuit has a typical power dissipation of 75mW, 30 to 40 times less than that of a conventional ECL circuit.This dveice is widely used in telecommunication, instrumentation and frequency synthesizers.