VHDL语言在电子设计自动化中的应用

Application of VHDL in EDA

介绍了VHDL语言及其基本特点和VHDL强大的仿真工具Active VHDL ,并结合例子描述了VHDL语言在数字电路设计仿真调试阶段所起的重要作用 ,仿真通过之后需要进行综合才能完成设计工作。结合使用VHDL的仿真和综合工具进行电子设计自动化设计的实际芯片取得了令人满意的结果。

The very high integrated circuit HW description language (VHDL), its basic features and one of its powerful simulation tool, Active VHDL, are introduced. With an example, The important role played by VHDL in the simulative test of digital circuit design is described. The synthesis is needed to complete the design after simulation. A real chip design by EDA with VHDL simulation and synthesis tools is successfully fulfilled and satisfied result is achieved.