摘要
通用并行CRC算法及其硬件实现方法 ,适用于不同的CRC生成多项式和不同的并行数据长度 ,与目前常用的查表法相比较 ,不需要存放余数表的高速存储器 ,减少了时延 ,并可以通过增加并行数据长度的方法来降低高速数据传送系统的CRC运算时钟频率 .
The principle and implementation of a general parallelcyclic,or CRC computing are described in the paper. Itis isissuitable for any generator polynomial and any parallel degree of generator polynomial between 1 and 32. Compared with Tablelookup algorithm,it need not the high speed RAM which was usedto store the remainder table, and decrease the delay. Thus, we can increase properly parallel degree to decrease the clockfrequency of CRC computing in highspeed digital systems.
出处
《西北民族学院学报(自然科学版)》
2002年第1期33-37,共5页
Journal of Northwest Minorities University(Natural Science )