摘要
随着集成电路的特征尺寸不断缩小 ,连线延迟成为决定电路性能的主要因素之一 ,减小连线网络复杂度已成为高层次综合算法的一个重要内容 .本文提出了一种同时进行资源分配和布局规划的算法 ,使用最小割 (Min Cut)算法对已调度的数据依赖图 (DFG)进行多路分割 ,实现了资源分配 ,同时又把分割的过程对应到Slicing结构的布局规划中 .在算法进行过程中可以不断利用前面步骤所提供的布局信息指导资源分配 ,从而有效的对连线进行优化 .
With the feature size of VLSI scaling down, interconnection delays begin to dominate the circuit performance. Interconnect nets reduction becomes an important part of high level synthesis. We present an algorithm which cope allocation and floorplan problems simultaneously, we use Min-cut method to multi-partition scheduled DFG, implementing resource allocation as well as mapping the partition procedure to Slicing structure based floorplan. During the partition procedure, floorplan information is used to direct allocation, thus interconnections are efficiently optimized. Design examples are presented to help concluding that our algorithm is very efficient.
出处
《电子学报》
EI
CAS
CSCD
北大核心
2002年第5期766-768,共3页
Acta Electronica Sinica
关键词
资源分配
布局规划
高层次综合算法
集成电路
Algorithms
Data processing
Electric network synthesis
Interconnection networks
Planning
Resource allocation