摘要
由于使用了 EDA工具 ,在设计过程中直接进行时序和逻辑验证 ,避免了系统设计过程中可能发生的错误。论述了基于 CPL D的中断控制器 IP设计。用电路图编辑了整个设计 ,并在 Altera公司 EPM712 8SL C84 - 6上实现了该中断控制器。
The IP design of interrupt controller based on CPLP is described With EDA tools, clock and logic verification is directly used in the course of design, the fault could be avoided The structure of the interrupt controller is edited by electric graphic, and it was implemented in EPM7128SLC84-6
出处
《现代电子技术》
2002年第6期19-20,23,共3页
Modern Electronics Technique