基于虚拟制造技术的集成电路工艺设计优化

Optimizing IC Process Design with Virtual Fabrication

采用虚拟制造技术对 0 .8μm双阱 LPLV CMOS工艺进行优化 ,确定了主要的工艺参数。在此基础上 ,对全工艺过程进行仿真 ,得到虚拟制造器件和软件测试数据 。

A 0 8 μm dual well LPLV CMOS process is optimized and major process parameters are defined using Virtual Fabrication technique The whole process is simulated and test data for virtual devices are obtained The results are in good agreement with the measured data