基于神经网络的片上互连线电感提取法

On-chip Inductance Modeling of VLSI Interconnects Based on Neural Networks

通过将具有自学习能力和记忆功能的神经网络应用于平行导体间的电感计算 ,结合移动窗口方法搜索作用域 ,实现片上互连寄生电感参数提取。仿真例子表明 ,此方法能够快速、有效地实现电感提取 ,可作为 VLSI互连线性能分析。

Cooperating with shift window method used to search interaction areas, a quick on chip parasitic inductance extractor based on neural networks, which has good memory and the capability of self learning, is presented Simulation results show that this method can estimate inductances quickly and efficiently, and may be used as a good guidance for designing and analyzing VLSI interconnects