全扫描结构可测性设计方法的研究

Research on the Full-Scan Method in Design for Testability

探讨了在 Synopsys软件中用全扫描结构实现数字电路可测性设计中遇到的问题及解决方法 ,如扫描结构的基本结构、测试的时序等问题。扫描结构对电路本身的结构有严格的要求 。

Application of scanning method in the design for testability (DFT) of digital system is described in the paper Problems with DFT, such as the basic scanning structure and test sequence,are discussed In scanning method, strict regulations are imposed on the original circuit structure of the chip Restrictions of the scanning structure on the circuit structures and revision of a circuit to conform to the regulations are discussed in particular