硅验证及其实践

Verification and Application of Silicon

用于可编程逻辑器件（ＰＬＤ）的电子设计自动化软件将用户的电子设计最终生成熔丝映射文件如ＪＥＤＥＣ、ＳＶＦ文件，并下载到ＰＩＤ器件中去。随着器件的密度越来越大，在ＰＬＤ ＥＤＡ软件的质量保证中测试熔丝映射文件的正确性对测试工程师来说是一个挑战，而硅验证即为一种重要的方法。介绍了硅验证的地位。

The PLD EDA software generates fuse map file such as JEDEC file and SVF file from the user' s design and downloads it into the PLD device. With the PLD density becomes higher and higher, it is challengable to verify the fuse map file in the quality assurance of the PLD EDA software, and the Silicon Verification is an important method. The goals and the process flow of the Silicon Verification and the detail example are discussed here.