IEEE1149.1测试存取口与器件可测性同步的实现

Synchronizing the IEEE 1149. 1 TAP for Chip-Level Testability

提出了加强测试存取口（ＴＡＰ）功能的一种方法，使之可以随两个时钟工作，一个用于控制与ＩＥＥＥ１１４９．１标准相兼容的操作，另一个控制器件所固有的可测试特性．这个方法给设计和利用器件的可测性特性带来了许多优越性．

This article presents a method that enhances the test access port(TAP) to let it operate with two clocks: one standard - compliant external test clock used for accessing IEEE 1149. 1 - compliant features and another alternative internal clock running synchronous to the chip clock while accessing chip manufacturing test features. The architecture also permits flexibility in selecting the test access speed to accommodate tester limitations.