数字专用集成电路设计中的SystemC建模验证方法

The Verification Method of SystemC Modeling in Digital ASICs Design

针对当前数字专用集成电路设计中的验证瓶颈,提出了一种基于SystemC电路行为建模与测试控制技术的专用集成电路验证方法,并应用到网络调度芯片的具体验证实验中.实验数据表明:由于采用软件建模与控制技术,该方法在缩短验证周期、提高验证可靠性、精确判断验证程度以及有效集成各类验证环境等方面均明显优于传统RTL验证方法.

With respect to the verification bottleneck of current digital ASICs design, a RTL verification method is presented based on SystemC ASIC behavior modeling and test controlling technology. The use of this method in an actual queue scheduler ASIC is also illustrated and analyzed for detail. The experimental results reveal that with the advantage of software modeling and controlling technology, the process of our ASIC verification is obviously superier to the traditional process in condensing period, enhancing reliability and integrating other evaluating environments.