面向功耗优化的伪随机测试矢量生成

The Pseudorandom Test Pattern Generation Oriented to Power Dissipation

随着集成电路设计复杂度和工艺复杂度的提高 ,集成电路的测试面临越来越多的挑战 ,内建自测试作为一种新的可测性设计方法 ,能显著提高电路中随机逻辑的可测性 ,解决一系列测试难题 ,但它同时也引起了测试功耗问题。本文提出了一种面向功耗优化的伪随机测试向量生成方法 ,在保证故障覆盖率的条件下 ,大大降低了测试功耗。

As the increase of Integrated Circuits′ design complexity and process complexity, the Integrated Circuits′ test are faced with more and more challenges. Built in self test, as a new method of design for testability, can prominently improve the testability of random logic in the circuits, resolve a series of test problem, but bring the power dissipation problem during test mode. In this paper a new test pattern generation method is proposed, which can greatly reduce the power dissipation during test mode and has no impact on the fault coverage.