摘要
本文介绍了采用Σ-Δ调制技术的小数分频PLL频率合成器。为了提高分频信号的质量和减少小数分频器的小数杂散,我们采用了高阶Σ-Δ调制技术原理。本文还提出了采用这种原理的具体电路实现方式。
A PLL frequency synthesizer based on fractional frequency division and Σ-Δ technique is introduced. In the effort to improve the quality of frequency division signals, high-order Σ-Δ modulation technique is employed, including. Over-sampling A/D conversion. The spectrum of error energy is compressed as to eliminate the fractional synthesis error energy from the carrier. Practical circuits based on the proposed principle are also given.
出处
《电路与系统学报》
CSCD
2002年第2期67-71,共5页
Journal of Circuits and Systems
关键词
∑-Δ调制
小数分频
小数杂散
时分复用
Σ-Δ Modulation
fractional-N synthesis
fractional spur
time-division
