7Moore G E. Cramming more components onto integrated circuits [J]. Electronics, 1965; 38(8): 114-117.
8Jing T, Hong X-L, Cai Y-C, et al. Challenges to data-path physical design inside SOC [J]. Chinese Journal of Semiconductors, 2002; 23(8): 785-793.
9IEEE Computer Society. IEEE Std 1364-2001: IEEE Standard Verilog Hardware Description Language[M]. New York, USA: The Institute of Electrical and Electronics Engineers, Inc. , 2001.
10Cadence Design Systems Inc. Envisia LEF/DEF Language Reference [M]. Version 5.3, San Jose, USA:Cadence Design Systems Inc. , 2000.