基于时钟设计的异步时序逻辑电路设计法

Design of Asynchronous Sequential Logic Circuit Based on Design of Clock Signal

基于时钟设计的异步时序逻辑电路设计法 ,根据电路状态转换规律 ,立足电路中各位触发器时钟设计 ,使电路完成所要求的逻辑功能 ,从而避免了求解电路状态方程、驱动方程。

The article introduces the design of asynchronous sequential logic circuit based on design of clock signal. According to the state transition regulation of the circuit, it only designs the clock signal for each flip-flop in the circuit and makes it realizes the logic function demanded. This method aviods looking for the circuit's state and excitation functions.