Verilog HDL语言在FPGA/CPLD系统设计中的几个原则

Rules of CPLD/FPGA System Design Based on Verilog HDL

根据 FPGA/ CPL D硬件结构的特点 ,从系统设计的实际出发 ,提出了利用 Verilog HDL 进行 FPGA/CPL D设计的一些描述风格的基本原则 ,这些原则中 ,有些是传统电路设计中不存在的 ,但是对设计的性能具有直接的影响 .这些原则也可以用于指导用原理图进行设计 .

This paper gives the rules of Verilog HDL description styles in the FPGA/CPLD system design base on the architecture of PLD. The rules, part of which are beyond the traditional methods, affect the preference of the results directly. Though the discussion bases on HDL, the rules can be applied to direct schematic base design.