SOC中Data-Path布图设计面临的挑战(英文)

Challenges to Data-Path Physical Design Inside SOC

目前所设计的系统级芯片 (SOC)包含有多个 data- path模块 ,这使得 data- path成为整个 G大规模集成电路 (GSI)设计中最关键的部分 .以往的布图理论及算法在许多方面已不能满足 data- path布图设计的需要 ,这主要是由于传统的布图工具没有考虑 data- path所特有的电路结构特点 . Data- path具有规整的位片结构 ,具有很高的性能指标要求 ,如对于时延、耦合效应和串扰等性能都有严格的要求 .此外 ,data- path中还存在大量成束状结构的 BUS线网 .文中提出了 data- path布图设计所面临的挑战 .从介绍 data- path布图的基本问题入手 ,重点分析了 data- path布图设计中的关键技术 ,并在讨论已有研究工作的基础上针对不同的布图阶段提出了可行的技术路线与设想 .

Previously,a single data-path stack was adequate for data-path chips,and the complexity and size of the data-path was comparatively small.As current data-path chips,such as system-on-a-chip (SOC),become more complex,multiple data-path stacks are required to implement the entire data-path.As more data-path stacks are integrated into SOC,data-path is becoming a critical part of the whole giga-scale integrated circuits (GSI) design.The traditional physical design methodology can not satisfy the data-path performance requirements,because it can not accommodate the data-path bit-sliced structure and the strict performance (such as timing,coupling,and crosstalk) constraints.Challenges in the data-path physical design are addressed.The fundamental problems and key technologies in data-path physical design are analysed.The corresponding researches and solutions in this research field are also discussed.