支持并行模拟的Verilog编译技术研究与实现

Verilog Compile Techniques in Support of Parallel Simulation

并行HDL模拟是加速大型复杂的VLSI系统模拟验证的有效方法,支持并行模拟的HDL编译技术是其中的关键技术。文章提出了一种支持并行模拟的Verilog编译技术,编译器将Verilog描述转换成C++代码,最后与并行模拟核心库编译链接生成可执行并行程序。文章将主要介绍编译器构成、代码生成方法和并行模拟核心库,该技术已经在并行Verilog模拟器ParaVer上实现。

Parallel HDL simulation is an efficient method to accelerate the verification process of large complex VLSI system design.HDL compilation technique that supports parallel simulation is the key technique.This paper presents a new Verilog compilation technique which has been implemented in parallel Verilog simulator -ParaVer.The compiler translates Verilog description into C++code,and generates executable parallel program after compiling and linking the C++code and parallel simulation kernel.This paper introduces the composition of the compiler,code generation method and Verilog parallel simulation kernel.