基于H.264快速半像素插值算法的VLSI实现

VLSI Implementation of Fast Half-Pixel Interpolation Algorithm Based on H. 264

提出一种快速半像素插值算法的VLSI硬件结构,该结构充分利用中间数据,有效地降低了分像素运动估计的计算量。采用Altera FPGA开发平台进行验证,系统可稳定地工作在135 MHz时钟频率下,并实时编解码1080P@25fps高清视频,满足系统的实时性要求。

A fast interpolation VLSI hardware architecture based on half-pixel is proposed to reduce the half- pixel motion estimation complexity for its full use of process data. ALTERA FPGA platform is employed for validation, which shows that the system runs stable at 135 MHz with the ability of encoding a high resolution video of 1080P@25fps in real time, which meets the requirement of real time video encoding and decoding.