摘要
数字下变频是软件无线电的核心技术,随着通信技术的发展,如今对其处理速度要求越来越高。现提出了一种高性能的数字下变频硬件计算结构,使用CORDIC,流水线划分,重定时等技术来优化数字下变频各个模块的硬件结构。通过和传统设计方案的实验比较,证明了本方案能在将FPGA总体资源使用等效门数减少29.54%的情况下,将最高数据吞吐率提升6.74倍。
Digital down converter （DDC） is the core technology of software radio. As the development ofwireless communication, there is a growing demand in the calculate speed of DDC. This paper presents ahigh performance DDC hardware structure. CORDIC, pipelining, retiming are used to optimize eachhardware unit in it. The experiment results show that in comparison with the traditional DDC structure,the optimized DDC can reduce FPGA design equivalent gate count by 29.54% and increase the maximumdata throughput by 6.74 times.
出处
《信息技术》
2014年第7期94-97,共4页
Information Technology
关键词
数字下变频
结构优化
流水线
重定时
digital down converter
structure optimization
pipeline
retiming
