多通道抽取FIR滤波器的FPGA高效实现

High Efficiency Implementation of FPGA-based Multi-channel Decimation FIR Filter

针对多频连续波雷达的技术要求,提出了一种基于FPGA的多通道抽取FIR滤波器的高效实现方案。该方案采用滤波器的对称结构、抽取的高效结构、流水线和时分复用技术等对传统的滤波器设计方法进行了改进,并利用Quartus II、Matlab以及ModelSim等软件对该方案进行了仿真验证,最后给出结果比较和性能分析。仿真结果表明该方案在系统速度没有增加的基础上,节省了大量的FPGA资源,易于工程实现。

Aiming at technical requirements for the Multi-frequency Continuous Wave （ MFCW） Radar, a high efficiency implementation plan for FPGA-based multi-channel decimation FIR filter is proposed. This plan uses symmetrical structure of filter, high efficiency structure of decimation, pipelining and Time Division Multiplexing technique to improve methods of designing the traditional filters. The design is simulated with the softwares like Quartus II, Matlab and ModelSim, the result comparison and performance analysis is provided finally. The simulation result shows that this design has saved a great number of FPGA resources on the basis of stabilization in system speed, and it’ s easy to implement in project.