一种基于CMOS工艺的高速采样保持电路的设计

Design of a High Speed Track/Hold Circuit in CMOS Process

设计了一种基于CMOS工艺的高速采样保持电路。该电路采用了开环双路双差分结构。详细分析了引起电路非线性的原因,并采用了新的结构来提高电路的线性度。仿真结果表明,在电源电压为1.9V,输入信号频率为393.75MHz,采样率为1.6GS/s,负载为0.5pF时,该电路的无杂散动态范围(SFDR)为80.5dB,总谐波失真(THD)为-78.6dB,有效位为12.7位。该电路具有高采样率、高SFDR和较强驱动能力等优点。

The design of a CMOS high-speed track/hold circuit is presented.The circuit adopts open-loop and dual-path-dual-differential structure.The nonlinearity of the circuit is analyzed and new structures are used to improve the linearity.Simulation results show that the circuit＇s SFDR is 80.5dB,THD is-78.6dB,ENOB is 12.7bits with 393.75MHz input,1.9Vvoltage supply,0.5pF load and 1.6GS/s sample rate.The circuit features high sample rate,high SFDR and strong drive capability.