摘要
目前自激振荡线路驱动器由于极限环频率较低,在输入信号频率较高时,系统增益下降较大,由延时决定的自激振荡线路驱动器可提高极限环频率。本文分析了提高极限环频率后系统增益、线性度和功耗等的变化,并采用0.25μm CMOS工艺设计了一个VDSL线路驱动器进行验证。实验结果表明,提高极限环频率可减小高频输入信号时系统增益的下降,且在一定范围内可提高线性度,但过高的极限环频率会引入过大的电源噪声和地噪声,恶化线性度。
The low limit cycle frequency of the self-oscillating line driver makes the system gain decrease too much when the input signal frequency is high enough,which can be solved using the delay-determined self-oscillating line driver by improving the limit cycle frequency.The impact of improving the limit cycle frequency on system gain,linearity and power consumption is analyzed.A VDSL line driver is realized to verify the analysis results.The experiment results show that improving the limit cycle frequency can ensure the stability of the system gain,and improve the linearity within a certain range.Whereas,if the limit cycle frequency is too high,the linearity will be deteriorated because of the fluctuation on power supply and ground.
出处
《微电子学》
CAS
CSCD
北大核心
2014年第3期305-309,共5页
Microelectronics
基金
国家自然科学基金资助项目(61274029)