期刊文献+
任意字段
题名或关键词
题名
关键词
文摘
作者
第一作者
机构
刊名
分类号
参考文献
作者简介
基金资助
栏目信息

Better-Than-Worst-Case Design: Progress and Opportunities

Better-Than-Worst-Case Design: Progress and Opportunities
原文传递
导出
摘要 Today, designers are forced to reduce performance and increase power requirements in order to reserve larger margins that are required due to the greater variability introduced by smaller feature sizes and manufacturing variations of modern IC designs. The better-than-worst-case design can both address the variability problem and achieve higher performance/energy efficiency than the worst-case design. This paper surveys the progress to date, provides a snapshot of the most representative methods in this field, and discusses the future research directions of the better-than-worst-case design. Today, designers are forced to reduce performance and increase power requirements in order to reserve larger margins that are required due to the greater variability introduced by smaller feature sizes and manufacturing variations of modern IC designs. The better-than-worst-case design can both address the variability problem and achieve higher performance/energy efficiency than the worst-case design. This paper surveys the progress to date, provides a snapshot of the most representative methods in this field, and discusses the future research directions of the better-than-worst-case design.
作者 丛京生 Henry Duwe Rakesh Kumar 李森
机构地区 ACM IEEE Computer Science Department Electrical and Computer Engineering Department
出处 《Journal of Computer Science & Technology》 SCIE EI CSCD 2014年第4期656-663,共8页 计算机科学技术学报（英文版）
基金 partially supported by the National Science Foundation of USA under Grant No.CCF-0903541
关键词 better-than-worst-case error resilience VARIABILITY better-than-worst-case, error resilience, variability
分类号 TN402 [电子电信—微电子学与固体电子学] TB47 [一般工业技术—工业设计]
  • 相关文献

参考文献24

  • 1Cong J, Minkovich K. Logic synthesis for better than worstcase designs. In Proc. Int. Symp. VLSI Design, Automation and Test, April 2009, pp.166-169.
  • 2Cong J, Minkovich K. Mapping for better than worst-case delays in LUT-based FPGA designs. In Proc. the 16th FPGA, Feb. 2008, pp.56-64.
  • 3Austin T, Bertacco V, Blaauw D, Mudge T. Opportunities and challenges for better than worst-case design. In Proc. ASP-DAC, Jan. 2005, pp.2-7.
  • 4Ernst D, Kim N S, Das S et al. Razor: A low-power pipeline based on circuit-level timing speculation. In Proc. the 36th MICRO, Dec. 2003, pp.7-18.
  • 5Liu Y, Ye R, Yuan F et al. On logic synthesis for timing speculation. In Proc. ICCAD, Nov. 2012, pp.591-596.
  • 6Kahng A B, Kang S, Kumar R, Sartori J. Recovery-driven design: A power minimization methodology for error-tolerant processor modules. In Proc. the 47th DAC, June 2010, pp.825-830.
  • 7Kahng A, Kang S, Kumar R, Sartori J. Designing a processor from the ground up to allow voltage/reliability tradeoffs. In Proc. the 16th HPCA, June 2010.
  • 8Narayanan S, Sartori J, Kumar R, Jones D. Scalable stochastic processors. In Proc. DATE, Mar. 2010, pp.335-338.
  • 9Lingamneni A, Enz C, Nagel J L et al. Energy parsimonious circuit design through probabilistic pruning. In Proc. DATE, Mar. 2011.
  • 10Ye R, Wang T, Yuan F et al. On reconfiguration-oriented approximate adder design and its application. In Proc. ICCAD, Nov. 2013, pp.48-54.
Journal of Computer Science & Technology
2014年 第4期

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部