摘要
Recent years,the hardening of combinational circuits is becoming a common concern.Unlike the transistor-level hardening technique,the cell-level hardening technique,a divide and conquer strategy,can substantially make use of some typical character in the cell-circuit module to mitigate single event transient(SET)sensitivity.The mirror image(MI)technique proposed in this paper can adequately enhance the charge sharing in those cell-circuits with stage-by-stage inverter-like structure.3D TCAD mixed-mode simulation have been performed in 65 nm twinwell bulk CMOS process,the results indicate that the MI technique can almost reduce the SET pulse width from the anterior-stage PMOS over 25%,and can mitigate the SET pulse width from the posterior-stage PMOS about 10%.The MI technique,a represent of the cell-level technique,may be the future of the hardening of combinational circuits.
Recent years, the hardening of combinational circuits is becoming a common concern. Unlike the transistorlevel hardening technique, the celllevel hardening technique, a divide and conquer strategy, can substantially make use of some typical character in the cellcircuit module to mitigate single event transient （SET） sensitivity. The mirror image （MI） technique proposed in this paper can adequately enhance the charge sharing in those cell-circuits with stage-by-stage inverterlike structure. 3D TCAD mixed-mode simulation have been performed in 65 nm twinwell bulk CMOS process, the results indicate that the MI technique can almost reduce the SET pulse width from the anteriorstage PMOS over 25 %, and can mitigate the SET pulse width from the posteriorstage PMOS about 10 %. The MI technique, a represent of the cell-level technique, may be the future of the hardening of combinational circuits.
基金
supported by the National Natural Science Foundation of China (61376109)
关键词
单事件
技术
细胞
瞬态
镜像
组合逻辑电路
次布
CMOS工艺
Single event transient （SET）
Chargesharing
Stagebystage structure
Mirror image（MI）
Cell-level hardening
