单器件时钟负载限制竞争RAM锁存器设计(英文)

A Single Device Clock Loaded Contention Constrained RAM Latch Design

提出一种新型RAM锁存器,通过引入并行充电支路,可避免开关电流和充电速度之间的矛盾。与传统结构相比,新结构不仅能提高充电速度,而且能降低短路功耗。此外,新结构中时钟负载只有一个MOS管,能有效降低时钟功耗。Hspice仿真结果表明,新的RAM n-锁存器和p-锁存器速度分别提高12.8%和25.5%,功耗延迟积分别降低19.8%和26.9%。

A new structure of RAM type latch is proposed in which parallel charging branches are used to solve the contradiction of the switching current and the charging speed. Compared with the conventional structure, new latch can maintain a relatively high rate of charging and reduce the short-circuit power. Furthermore only one MOS transistor is needed as clock load, saving the power consumption of clocking. HSPICE simulation results show that the proposed RAM n-Latch and p-Latch exhibits 12.8% and 25.5% speed improvement, 19.8% and 26.9% PDP （power-delay product） reduction compared to reported structure.