期刊文献+

漏极接触孔到栅间距对GGNMOS保护器件的影响

Influence of drain contact to gate space on the characteristic of the GGNMOS protection device
下载PDF
导出
摘要 研究了不同漏极接触孔到栅间距对深亚微米单叉指栅接地N型金属氧化物半导体静电放电保护器件性能的影响,并分析了相关物理机制.基于中芯国际0.18μm互补金属氧化物半导体工艺进行流片,并进行传输线脉冲测试,得到了不同漏极接触孔到栅间距(DCGS)值的保护器件单位宽度失效电流水平的变化趋势.结合器件仿真,分析了保护器件的电、热分布情况.研究结果表明,DCGS值的增大,使电流密度峰值向远离沟道的方向移动,从而降低了尖端放电的风险.同时,当DCGS值增大到一定阈值时,由于漏区与衬底温度达到平衡,因此失效电流水平出现饱和趋势. Based on the test data,the influence of DCGS on the single finger GGNMOS ESD protection device is investigated.The changing tendency of the failure current level is given by the TLP test under various layout parameter conditions realized in the SMIC 0.1 8μm CMOS process.Electrical and thermal distribution is detailed based on the device simulation.The results show that the peak value of the current density is moved in the opposite direction to the channel, which lowers the risk of LDD discharge. Meanwhile,the failure current level shows the saturation tendency because of the heat balance of the drain and substrate region which appears when the DCGS is raised to the threshold value.
出处 《西安电子科技大学学报》 EI CAS CSCD 北大核心 2014年第4期26-30,共5页 Journal of Xidian University
基金 国家部委预研究基金资助项目(9140A23060111) 陕西省科技统筹创新工程计划资助项目(2011KTCQ01-19) 中央高校基本科研业务费专项资金资助项目(K5051325011)
关键词 漏极接触孔到栅间距 静电放电 栅接地N型金属氧化物半导体 drain contact to gate space (DCGS) electrostatic discharge (ESD) gate grounded NMOS(GGNMOS)
  • 相关文献

参考文献12

  • 1Fukasaku K,Yamazaki T,Kanno M.Origin of It2 Drop Depending on Process and Layout with Fully Silicided GGMOS[C]//Electrical Overstress/Electrostatic Discharge Symposium.Piscataway:IEEE,2011:1-6.
  • 2Iyer N M,Jiang H,Yap H K,et al.Engineering Fully Silicided Large MOSFET Driver for Maximum It1 Performance[C]//Electrical Overstress/Electrostatic Discharge Symposium.Piscataway:IEEE,2010:1-6.
  • 3Iyer N M,Jiang H,Yap H K,et al.ESD Engineering Fully Silicided Large MOSFET Driver for Maximum It1 Performance[J].IEEE Transactions on Device and Materials Reliability,2011,11(4):516-521.
  • 4刘红侠,刘青山.0.18μm CMOS工艺下的新型ESD保护电路设计[J].西安电子科技大学学报,2009,36(5):867-870. 被引量:7
  • 5杜鸣,郝跃.CMOS工艺中栅耦合ESD保护电路[J].西安电子科技大学学报,2006,33(4):547-549. 被引量:6
  • 6Chen T,Ker M.Analysis on the Dependence of Layout Parameters on ESD Robustness of CMOS Devices for Manufacturing in Deep-submicron CMOS Process[J].IEEE Transactions on Semiconductor Manufacturing,2003,16(3):486-500.
  • 7Amerasekera E A,Duvvury C,Anderson W,et al.ESD in Silicon Integrated Circuits[M].New York:Wiley,2002:328.
  • 8吴晓鹏,杨银堂,高海霞,董刚,柴常春.基于深亚微米工艺的栅接地NMOS静电放电保护器件衬底电阻模型研究[J].物理学报,2013,62(4):424-430. 被引量:5
  • 9Oh K,Duvvury C,Banerjee K,et al.Investigation of Gate to Contact Spacing Effect on ESD Robustness of Salicided Deep Submicron Single Finger NMOS Transistors[C]//Reliability Physics Symposium Proceedings.Piscataway:IEEE,2002:148-155.
  • 10Mohan N,Kumar A.Modeling ESD Protection[J].IEEE Potentials,2005,24(1):21-24.

二级参考文献14

  • 1杜鸣,郝跃.CMOS工艺中栅耦合ESD保护电路[J].西安电子科技大学学报,2006,33(4):547-549. 被引量:6
  • 2Ker M D. Whole-chip ESD Protection Design with Efficient VDD-to-VSS ESD Clamp Circuits for Submieron CMOS VLSI[J]. IEEE Trans on Electronic Devices, 1999, 46(1): 173-183.
  • 3Andrea C, Simone G, Augusto T, et al. Electrostatic Discharge Effects in Ultrathin Gate Oxide MOSFETs[J]. IEEE Trans on Devices and Materials Reliability, 2006, 6(1):87-94.
  • 4Smith J C, Boselli G. A MOSFET Power supply clamp with feedback enhanced triggering for ESD protection in advanced CMOS technologies [J]. Microelectronics Reliability, 2005, 45(2): 201-202.
  • 5Ker M D, Chen J H. Self-Substrate-Triggered Technique to Enhance Turn-On Uniformity of multi-Finger ESD Protection Devices [J]. IEEE Solid-State Circuit, 2006, 41(11) :2601-2609.
  • 6Ker M D, Lin K H. The Impact of Low-holding-voltage Issue in High-voltage CMOS Technology and Design of Latchup- free Power-rail ESD Clamp Circuit for LCD Driver IC [J]. IEEE Solid-State Circuit, 2005, 40(8) :1751-1759.
  • 7Chou H M, Lee J W, Li P Y. A Floating Gate Design for ESD Protection Circuits[J]. The VLSI Journal, 2007, 40(2):161-166.
  • 8Feng Haiqiang, Chen Guang, Zhan Rouying, et al. A Mixed-mode ESD Protection Circuits Simulation-design Methodology [J]. IEEE Solid-State Circuit, 200a, 38(6): 995-1006.
  • 9Ker M D, Chang W J. ESD Protection Design with On-chip ESD Bus and High-voltage-tolerant ESD Clamp Circuit for Mixed-voltage I/O Buffers [J]. IEEE Solid-State Circuit, 2008, 55(6): 1409-1416.
  • 10孙自敏,刘理天,李志坚.深亚微米PESD MOSFET特性研究及优化设计[J].Journal of Semiconductors,1998,19(11):851-856. 被引量:4

共引文献13

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部