优化SOC测试时间的扫描链平衡及NSGA-Ⅱ设计

NSGA-Ⅱ design and scan chain balance of optimizing the SOC test time

片上系统SOC测试时间很大程度上取决于Wrapper和测试访问机制TAM(test access mechanism)的设计。为了优化SOC测试时间,主要对Wrapper和TAM进行设计,降低单个核的测试应用时间靠优化的Wrapper,在差值二次分配平衡扫描链的基础上,对TAM进行划分,以测试时间和TAM宽度为目标进行优化,运用非支配排序目标遗传算法(NSGA-II)对模型进行求解,并采用ITC02标准电路中的d695电路为实例进行验证,结果表明该方法与基于SA、ILP算法相比,能够在降低SOC测试时间上获得较为理想的效果,并且降低相应的测试功耗,证明本实验方法切实可行。

The test time of the system on chip（SOC）is dependent on the design of the wrapper and test access mechanism（TAM）to a great extent.In order to optimize the SOC test time,the Wrapper and TAM（test access mechanism）are designed to reduce the single cores test operation time.Based on applying the difference secondary allocation method to balance the scanchain,the TAM is divided.This paper is aimed at the testing time and TAM width,and the model will be solved by using NSGA-II（non-dominated sorting genetic algorithm II）.Then,taking the d695circuit as an example from the ITC02standard circuits,compared with the SA（simulate anneal）and ILP（integer linear programming）algorithm,the experiment datas show that the better results can be achieved on the SOC test time optimization,and on the relevant test power as well.It provd that themethod is practicable.