基于异或门自选通的低功耗时钟树综合方案

Low Power Clock Tree Synthesis Depending on XOR Self-gating

本文介绍一种降低时钟网络功耗的方法。该方法基于电路中寄存器本身的状态值,在采用异或门进行自选通后构建时钟树结构,从而减少时钟信号额外翻转,降低芯片功耗。将该方法应用于一款基于SMIC0.18μmEflash 2p4m工艺下的非接触式智能卡芯片的物理设计。仿真结果表明,与传统时钟树综合方法相比,芯片功耗降低了10.7%。

The paper value of flip-flops in signal＇ introduces a method to decrease the power consumption of clock network. It is based on the state the circuit and uses XOR self-gating to build the clock tree for the purpose of decreasing clock s extra smitching and circuit＇ s power consumption. This method is applied to a contactless smart card chip based on SMIC 0.18 μmEflash2p4m process. The simulation result indicates that the chip＇ s power consumption has reduced 10.7% comparing to the traditional clock tree synthesis.