期刊文献+

基于BWDSP100的传播分簇算法研究与实现 被引量:4

Research and Implementation of Propagation Cluster Algorithm Based on BWDSP100
下载PDF
导出
摘要 BWDSP100是一款SIMD和VLIW架构高性能DSP,它的指令级并行性主要通过指令分簇和软件流水来实现。本文针对BWDSP100的特点,提出了一种新的分簇算法——传播分簇,该算法考虑了负载均衡和特殊ABI规则,不会产生簇间转移指令。实验结果表明,该分簇方法在Open64编译器上的实现可以取得比传统方法更好的效果。 BWDSP100 is a high performance DSP with SIMD and VLIW features. Its ILP is acquired through cluster- ing and software pipeline. This paper puts forward a new cluster algorithm - Propagation Cluster, which considers load balance and special ABI rules, and doesn' t generate move operations between clusters. The experimental results show that this method' s implementation on Open64 compiler can take better effect than traditional methods.
出处 《中国集成电路》 2014年第8期24-28,共5页 China lntegrated Circuit
关键词 数字信号处理器 超长指令字 指令级并行 分簇 Digital Singal Processor ( DSP ) Very Long Instruction Word ( VLIW ) Instruction Level Parallelism ( ILP ) Cluster
  • 相关文献

参考文献1

二级参考文献14

  • 1Fisher J.Very long instruction word architectures and the ELI-512[C].Proceedings of the Tenth Annual International Symposium on Computer Architecture,Stockholm,Sweden,1983,140-150.
  • 2Faraboschi P,Fisher J,Young C.Instruction scheduling for instruction level parallel processors[C].Proceedings of the IEEE,2001,89(11):1638-1659.
  • 3Kim J et al.Experience with a retargetable compiler for a commercial network processor[C].Proceedings of the 2002 International Conference on Compilers,Architecture,and Synthesis for Embedded Systems,Grenoble,France,2002,178-187.
  • 4S Rajagopalan et al.A retargetable VLIW compiler framework for DSPs with instruction level parallelism[J].IEEE Trans.on Computer-Aided Design,2001,20(11):1319-1328.
  • 5Shannon C J.The IMPACT SC140 code generator[D].MS Thesis,Department of Electrical and Computer Engineering,University of Illinois,Urbana IL,2002.
  • 6Chakrapani L N et al.Triceps:enhancing the trimaran compiler infrastructure for strongARM code generation[R].CREST Technical Report:CREST-TR-01-01.
  • 7Leupers R.Instruction scheduling for clustered VLIW DSPs[C].IEEE PACT 2000,291-300.
  • 8Lapinskii V S et al.Cluster assignment for high-performance embedded VLIW processors[J].ACM Transactions on Design Automation of Electronic Systems,2002,7(3):430-454.
  • 9Jang S et al.A code generation framework for VLIW architectures with partitioned register banks[C].In:Proceedings of the Third International Conference on Massively Parallel Computing Systems (MPCS),1998,61-69.
  • 10Chang P P et al.IMPACT:an architectural framework for multiple-instruction-issue processors[C].ISCA 1991,266-275.

共引文献6

同被引文献18

  • 1景晓军,方滨兴.SIMD计算机发展概述[J].计算机科学,1995,22(3):4-8. 被引量:2
  • 2University of Houston. Overview of the open64 Com- piler Infrastructure[EB/OL].[2010-09-12]. http://www2.es.uh.edu/-dragon/Documents/open64-doc .pdf.
  • 3SGI Inc. WHIRL intermediate language specification [E B/OL]. http://op en64. sourc eforge, net, 2006.
  • 4Vernon Turner. White Paper Intel Announces Xeon Proces- sor with 64 - Bit Extensions[EB/OL]. [2014 - 12]. http:// developer, intel, com/technology/64bitextensions/IDC_Intel_ Xeon_Whitepaper. pdf.
  • 5University of Houston. Overview of the open64 Compiler In- frastructure[ EB/OL]. [ 2014 - 12]. http://www2, cs. uh. edu/ dragon/Documents/open64 -doc. pdf.
  • 6SGI Inc. Whirl intermediate language specification[EB/OL]. [2014 - 12]. http..//open64, sourceforge, net.
  • 7Briggs P, Cooper K, Torczon L. Improvements to Graph Coloring Register Allocation[J]. ACM Transactions on Pro- gramming Languages and Systems, 1994,16(3):428- 455.
  • 8CETC38.BWDSPl00硬件用户手册[R].合肥:中国电子科技集团第三十八研究所,2011:1-2.
  • 9CETC38.BWDSPl00软件用户手册[R].合HE:中国电子科技集团第三十八研究所,2011:181-191.
  • 10SUI Y. Open64 introduction [ EB/OL]. [ 2015- 03- 17]. http:// www. cse. unsw. edu. au/- ysui/saber/open64, pdf.

引证文献4

二级引证文献4

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部