基于FPGA实现的SIRF模块级流水线设计

The Module-Level Pipelining Design of SIRF Based on FPGA

针对粒子滤波算法是计算量大、实时性差,难于硬件实现的特点,本文提出了用于目标跟踪问题的样本-重要性-重采样粒子滤波算法(SIRF)的模块级流水线设计方法。SIRF算法最重要的部分是数据中心,它负责处理模块之间大量的数据传输。整个滤波器使用模块级流水线设计,主要包括粒子生成模块、粒子更新模块、重采样模块、输出生成模块,该设计大大简化了设计流程。模块级流水线通过分布式控制器来实现同步执行,该控制器控制各个处理模块的数据生成和传输。最后利用Xilinx FPGA验证了该滤波器的实时性。

The main drawback of particle filter is the large computation and poor real-time performance.Thus,it is difficult to implement by hardware.The design of module-level pipeline is presented,which is based on the sample importance resampling（SIR） particle filter for bearings-only tracking problem.The most important part of SIRF is data center,which is responsible for processing large amount of data transfer among blocks.The entire design of filter is using module-level pipeline which greatly simplifies the design process,including particle generation,particle update,resampling and output generation.The module-level pipeline achieves synchronization through distributed controller which controls the data generation and transmission.Finally,by using Xilinx FPGA,it can verify the real-time performance of the filter.