隔离型达林顿管静态漏电失效分析

Failure Analysis on Isolated Darlington Transistor with the Static Leakage-Current

分析了半导体器件静态漏电对高可靠设备造成的危害。对比了失效器件在不同偏压条件下的测试结果,结合器件芯片版图的设计特点以及制造工艺特点,对隔离型达林顿管静态漏电的失效现象进行了分析,通过故障树分析,排除了外部沾污、静电损伤、过电应力损伤等使用问题导致器件失效的可能性,提出了器件出现异常静态漏电流是因为采用扩散方法制作的pn结深度不足导致的假设,并利用磨角染色法证明了失效芯片隔离岛隔离墙pn结深度不足的假设,并提出了改进意见。

The hazard of semiconductor devices static leakage for high-reliability equipment was analyzed, and the test results of the failure devices under different bias voltage conditions were also compared. According to the design features of device chip layout and the characteristics of manufacturing process, the failure of isolated darlington transistor with static leakage-current was analyzed. Through the failt tree analysis,the contamination, the electro-static discharge （ESD） or the electrical-over stress damage （ EOS ） was excluded to cause device failure. It was supposed that the static leakage-current was cased by insufficient depth of the pn junction which was made by diffusion technique and it was proved by grinding and staining the pn junction. Suggestions for improvement of the production process were also provided.